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| Ordering number : EN*5212 CMOS LSI LC78833M, 78833V Digital Audio 16-Bit D/A Converter with Built-In Digital Filters Preliminary Overview The LC78833M and LC78833V are CMOS 16-bit D/A converters with built-in 4x oversampling digital filters. Package Dimensions unit: mm 3036B-MFP20 [LC78833M] Functions and Features [Digital Filter Block] * 4x oversampling filters: Two FIR filter stages (33rd and ninth order) * De-emphasis filter: Supports a 44.1 kHz sampling frequency (fs). [D/A Converter Block] * Dynamic level shifting conversion 16-bit D/A converter * D/A converters for two channels (synchronized outputs) on a single chip * On-chip output operational amplifiers * System clock: 384fs * 5-V single-voltage power supply * Supports low-voltage operation (3.0 V) * Implemented in a Si gate CMOS process for low power. unit: mm 3175A-SSOP24 SANYO: MFP20 [LC78833V] Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0 V Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Operating temperature Storage temperature Symbol VDD max VIN max VOUT max Topr Tstg Conditions SANYO: SSOP24 Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -30 to +75 -40 to +125 Unit V V V C C SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN D3095HA (OT) No. 5212-1/11 LC78833M, 78833V Allowable Operating Ranges Parameter Supply voltage Reference voltage (high) Reference voltage (low) Symbol VDD Vref H Vref L Conditions min 3.0 VDD - 0.3 0 typ 5.0 max 5.5 VDD +0.3 Unit V V V Electrical Characteristics (1) at Ta = 25C, AVDD = DVDD = Vref H = 5.0 V, AGND = DGND = Vref L = 0 V, unless otherwise specified Parameter D/A converter resolution Total harmonic distortion Dynamic range Crosstalk Signal-to-noise ratio Full-scale output voltage Power dissipation Output load resistance Symbol RES THD DR CT S/N VFS Pd RL At fs = 44.1 kHz Pins 1 and 20 (1 and 24)*2 5 At 1 kHz and 0 dB*1 At 1 kHz, -60 dB At 1 kHz and 0 dB JIS-A 96 2.6 100 2.8 60 3.0 90 92 94 -85 Conditions min typ 16 0.08 max Unit Bit % dB dB dB Vp-p mW k Note: 1. Here, 0 dB means full scale. 2. Pin numbers in parentheses are for the LC78833V. Electrical Characteristics (2) at Ta = 25C, AVDD = DVDD = Vref H = 3.0 V, AGND = DGND = Vref H = 0 V, unless otherwise specified Parameter D/A converter resolution Total harmonic distortion Dynamic range Crosstalk Signal-to-noise ratio Full-scale output voltage Power dissipation Output load resistance Symbol RES THD DR CT S/N VFS Pd RL At fs = 44.1 kHz Pins 1 and 20 (1 and 24)*2 30 At 1 kHz and 0 dB*1 At 1 kHz, -60 dB At 1 kHz and 0 dB JIS-A 94 1.55 98 1.7 15 1.85 25 90 92 -85 Conditions min typ 16 0.10 max Unit Bit % dB dB dB Vp-p mW k Note: 1. Here, 0 dB means full scale. 2. Pin numbers in parentheses are for the LC78833V. No. 5212-2/11 LC78833M, 78833V Block Diagram DC characteristics at Ta = -30 to 75C, VDD = 3.0 to 5.5 V, VSS = 0 V Parameter Input high-level voltage (1) Input low-level voltage (1) Input high-level voltage (2) Input low-level voltage (2) Output high-level voltage Output low-level voltage Input leakage current Symbol VIH1 VIL1 VIH2 VIL2 VOH VOL IL Conditions Pins 5, 6, 7, 12, 13, and 14 (pins 6, 7, 8, 14, 16, and 17)* Pins 5, 6, 7, 12, 13, and 14 (pins 6, 7, 8, 14, 16, and 17)* Pin 8 (pin 9)* Pin 8 (pin 9)* Pin 9 (pin 11)*: IOH = -3 mA Pin 9 (pin 11)*: IOL = 3 mA Pins 5, 6, 7, 8, 12, 13, and 14 (pins 6, 7, 8, 9, 14, 16, and 17)*: VI = VSS, VDD -25 2.4 0.4 +25 0.7 VDD 0.3 VDD min 2.2 0.8 typ max Unit V V V V V V A Note: * Pins in parentheses apply to the LC78833V. AC Characteristics at Ta = -30 to 75C, VDD = 3.0 to 5.5 V, VSS = 0 V Parameter Clock pulse width Clock pulse period BCLK pulse width BCLK pulse period Data setup time Data hold time LRCK setup time LRCK hold time BCLK rise time BCLK fall time SYSCLK rise time SYSCLK fall time Symbol tCW tCY tBCW tBCY tDS tDH tLRS tLRH tBr tBf tSr tSf Conditions min 25 50 60 120 40 40 40 40 40 40 20 20 1000 typ max Unit ns ns ns ns ns ns ns ns ns ns ns ns No. 5212-3/11 LC78833M, 78833V Audio Input Waveforms Pin Assignments No. 5212-4/11 LC78833M, 78833V Pin Functions Pin No. LC78833M 1 2 -- 3 4 5 6 7 8 -- 9 10 11 12 -- 13 14 15 16 17 18 -- 19 20 LC78833V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin CH1OUT REFH NC Vref H AVDD LRCK DATA BCLK SYSCLK NC CKOUT DVDD TSTOUT TST NC EMP INITB DGND REFL AGND Vref L NC NC CH2OUT Channel 1 analog output High-level reference voltage Normally connected to AGND through a capacitor. No connection High-level reference voltage input Analog system power supply LR clock input A high level specifies channel 1 and a low level channel 2. Digital audio data input Accepts data in a two's complement MSB first format. Bit clock input System clock input (384fs) No connection System clock output (384fs) Digital system power supply Test output Test output This pin must be connected to DGND in normal operation. No connection De-emphasis filter on/off control input A high level specifies on and a low level off. This function supports a sampling frequency fs of 44.1 kHz. Initialization input. A low level input to this pin initializes the IC. Digital system ground Low-level reference voltage Normally connected to AGND through a capacitor. Analog system power supply Low-level reference voltage input No connection No connection Channel 2 analog output Description No. 5212-5/11 LC78833M, 78833V LC78833M/V Operation 1. Digital Filters The LC78833M and LC78833V perform the computations shown in the figure. * Oversampling The oversampling circuit in these ICs consists of two 2x interpolation filters (implemented as FIR filters) connected vertically. In particular, these ICs implement 4x oversampling by the vertical connection of two FIR filter stages, a 33rd-order stage and a ninth-order stage. See page 9 for the filter characteristics. * De-emphasis A first-order IIR filter is used for de-emphasis. The filter coefficients are optimized for a sampling frequency of 44.1 kHz. See page 9 for the filter characteristics when de-emphasis is applied. -- De-emphasis on/off switching De-emphasis is on when the EMP pin is high. De-emphasis is off when the EMP pin is low. 2. Digital Audio Data Input These ICs handle digital audio data in a 16-bit two's complement MSB first format. The 16-bit serial data is input to an internal register from the DATA pin on BCLK rising edges and read in on rising and falling edges of the LRCK signal. No. 5212-6/11 LC78833M, 78833V 3. Initialization These ICs must be initialized when power is first applied and when the system clock frequency is changed. Initialization is performed by applying a low level to the INITB pin. That low level must be held for at least one full cycle of the LRCK signal after the power supply voltage has stabilized and the SYSCLK, BCLK, and LRCK signals have been applied. When INITB is low, all 16 bits of the digital filter outputs go to 0, and the D/A converter outputs (CH1OUT and CH2OUT) go to the analog 0 level, which is a potential equal to (REFH +REFL)/2. 4. System Clock These ICs support a 384fs system clock. Apply a 384fs clock to the SYSCLK pin. * CKOUT pin The SYSCLK and CKOUT pins are related as shown in the figure below. No. 5212-7/11 LC78833M, 78833V 5. D/A Converter Block Channel 1 and channel 2 each include an independent 16-bit D/A converter and an output operational amplifier. These D/A converters use the dynamic level-shifting conversion scheme shown in the figure below. This scheme combines three conversion techniques, resistor string D/A conversion, PWM (pulse width modulation) D/A conversion, and level-shifting D/A conversion. No. 5212-8/11 LC78833M, 78833V * Resistor string D/A converter This 8-bit D/A converter uses a total of 256 (= 28) unit-resistance (R) resistors connected in series to voltage divide the potential applied to the ends of that resistor string into 256 equal intervals. Of these resistor-divided potentials, two adjacent potentials, V1 and V2, are selected by a switching circuit according to the value of the upper 8 bits (D15 to D8) of the data. These two potentials are output to the PWM D/A converter. Note that these potentials are related as follows: V2 - V1 = (VH - VL)/256 * PWM D/A converter This 4-bit D/A converter divides (by 16) the interval between the two potentials, V1 and V2, output by the resistorstring D/A converter. This circuit outputs one or the other of the V1 and V2 potentials from the CH1OUT (or CH2OUT) pin according to the value of the middle 4 bits (D7 to D4) of the data. * Level shifting D/A converter This 4-bit D/A converter is implemented by connecting the variable resistors VRH and VRL in series at the ends of the resistor-string D/A converter. The values of the VRH and VRL variable resistors are modified according to the value of the low-order 4 bits of the data as follows: -- The value of VRH + VRL is held fixed regardless of the value of the data. -- The values of VRH and VRL are changed in R/256 unit steps (where R is the value of the resistor-string D/A converter unit resistors) over the range zero to 15*R/256. This causes the resistor-string D/A converter V1 and V2 outputs to change in V/256 steps (where V = (VH - VL)/256) over the range 0 to 15 x V/256 according to the value of the lower 4 bits of the data. -- The Vref H/L and REFH/L pins The Vref H/L pins provide the reference voltage to the resistor string, and are normally connected to AVDD and AGND, respectively. REFH and REFL are each connected to AGND through a capacitor of about 10 F. The maximum output amplitude is acquired when Vref H is 5.0 V and Vref L is 0 V. The internal resistors RH and RL cause the output range to be between 0.7 V (minimum) and 3.5 V (maximum) (2.8 Vp-p) for 0 dB. Filter Characteristics (as calculated) 4x oversampling Ripple: Less than 0.1 dB Attenuation: -35 dB or lower No. 5212-9/11 LC78833M, 78833V Application Circuit Example Note 1. VDD and Vref H must be provided from a low-impedance, high-stability power supply, for example, a commercial three-terminal regulator or equivalent. 2. Since it is possible for the IC to latch up if there is a discrepancy between the pin 4 (AVDD) and pin 10 (DVDD) power supply power-on timing, application circuits should be designed so that there is no time difference between the application of these voltages. 3. Bypass capacitors of at least 47 F must be inserted between AVDD and AGND and between DVDD and DGND. These capacitor must be placed as close as possible to the IC. 4. Bypass capacitors of at least 10 F must be inserted between REFH and AGND and between REFL and AGND for reference voltage stability. No. 5212-10/11 LC78833M, 78833V Power On Timing 1. The analog power supply (AVDD) and the digital power supply (DVDD) should be applied (or removed) at the same time. 2. If a time difference between application of the analog and digital power supplies cannot be avoided, the timing must meet the following conditions: * The power supply power up (and power down) time differences must be under 3 ms. (See Figure 1.) * If the time difference exceeds 3 ms, the rise (fall) time of the power supply that rises (falls) first must be at least 5 ms, and the time difference must be under 50 ms. (See Figure 2.) Figure 1 Figure 2 s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 5212-11/11 |
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